Explore the full power-performance-area tradeoffs for arch/RTL/PD changes on a real silicon process. Open-source RTL, open PDK, real numbers.
Hello!
I'm Tejas — a Front-End RTL Integration Engineer in a Power-Performance-Area (PPA) Attainment team, where I dream up experiments to push our GPU Core IP to its absolute limits — and I wanted to bring that same energy to everyone.
PerfPerWatt lets you explore the full PPA tradeoff space of any piece of RTL on a real silicon process — open-source PDK, real EDA flow, real post-layout numbers. I use a RISC-V core as the example design here, but the flow works with any RTL you bring.
I hope you enjoy using it! If you have any suggestions, run into bugs, or have feature requests, I'd love to hear from you. Reach me on LinkedIn!
P.S. We're still a work in progress — more on the way!
Full OpenLane 2 flow on sky130A — from RTL to GDSII with real metrics.
Gate-level VCD-driven power with SPEF parasitics. Per-workload breakdown.
1,500+ synthesis runs exploring clock, area, and microarchitecture knobs.
Barrel shifter, 2-cycle ALU, clock gating, RV32E — see exactly what each change costs.
8 targeted benchmarks from idle to Dhrystone. Compare any two configs side-by-side.
Multi-corner V-F curves across SS/TT/FF. Find the sweet spot for your design.
Enter the passcode to access the dashboards.